Artificial line

ABSTRACT

An artificial line, particularly an artificial electric line, and specifically an artificial line having a constant group delay in a wide frequency range (octave bandwidths). The artificial line comprises two identical inductors of the magnitude L connected in series and having a mutual inductance M, and a capacitor of the magnitude C 1  over the inductors and a shunt capacitor C 2  to earth. The element values as a function of the cut-off frequency f c  and the characteristic impedance Z 0  are selected according to specific equations. The artificial line can then be realized as a continuously tunable artificial line or as a self-switched artificial line. The two types of artificial lines can also be cascade-coupled.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an artificial line, i.e. an artificialelectric line, and specifically an artificial line having a constantgroup delay in a wide frequency range (octave bandwidths). The inventionoriginates from delay lines for radar applications and will partly bedescribed in connection with such applications. However, the inventioncan be applied in other contexts where an artificial line having theachieved properties can be used. Therefore the inventor aims atprotecting the artificial line by a patent, based on its constructionand its properties and independently of the place where it is used.

2. Description of the Related Art

Advanced future radar installations will be based on phased arrayantennas. Since such antennas may have hundreds of modules, monolithicintegrated microwave circuits (MMIC) are necessary to minimize size andweight. Most prior-art microwave systems with phased array antennas areprovided with binary control devices. In large installations, a greatnumber of control wires will be involved since each element must becontrolled individually. If an analog control device could be used, muchwould be gained since only one control wire or a few control wires wouldbe required.

For installations requiring a great instantaneous bandwidth, phaseshifters cannot be used since they cause a change in the beam direction,phase squinting, and distortion of the pulses, pulse stretching.Therefore, the present invention instead uses a special embodiment of acontrollable delay element since such elements allowfrequency-independent beam steering. Prior-art controllable delayelements are digital, which causes losses. Besides they are expensive.

FIG. 1 shows a prior-art binary 4-bit delay element using single-poledouble-throw (SPDT) switches. Single-pole double-throw switches haveconsiderable losses, which means that the prior-art delay element all inall exhibits great losses. If in FIG. 1 the delay Δt is 8 ps, themaximum delay will be 120 ps.

SUMMARY OF THE INVENTION

The present invention solves the above problem by providing anartificial line with controllable delay and low losses and at a,relatively seen, low cost by being designed as an artificial line in theform of a two-port network with an essentially frequency-independentmirror impedance, which in a first state comprises two identicalinductors of the magnitude L, connected in series and having a mutualinductance M, and a capacitor of the magnitude C₁ over the inductors anda shunt capacitor C₂ to earth, the artificial line being adapted to givethe same group delay—the same amount of delay—in a wide frequency rangeby the element values as a function of the cut-off frequency f_(c) andthe characteristic impedance Z₀ being selected according to theinductance, mutual inductance and capacitance equations$\left\{ \quad {\begin{matrix}{{L\lbrack{nH}\rbrack} = {{107.4 \cdot 10^{- 3}}\frac{Z_{0}}{f_{C}\lbrack{GHz}\rbrack}}} \\{{M\lbrack{nH}\rbrack} = {{51.72 \cdot 10^{- 3}}\frac{Z_{0}}{f_{C}\lbrack{GHz}\rbrack}}} \\{{C_{1}\lbrack{pF}\rbrack} = {{27.85 \cdot 10^{- 3}}\frac{1}{Z_{0} \cdot {f_{C}\lbrack{GHz}\rbrack}}}} \\{{C_{2}\lbrack{pF}\rbrack} = {{318.3 \cdot 10^{- 3}}\frac{1}{Z_{0} \cdot {f_{C}\lbrack{GHz}\rbrack}}}}\end{matrix}\quad } \right.$

According to advantageous embodiments of the invention, the artificialline is a self-switched artificial line and can take a second state witha short delay by the capacitor C₁ being replaced by a short-circuit. Thecapacitor C₁ may be realized as a first switching element (FET 1, 4 a)optimized to take, in dependence on its control voltage, two distinctstates, a first state corresponding to a capacitance of the value C₁,which gives the artificial line a long delay, and a second statecorresponding to a short-circuit with low impedance, which gives theartificial line a short delay. The first switching element (FET 1, 4 a)may be realized as a first field effect transistor. Further, a secondswitching element (FET 2, 4 b) with properties corresponding to those ofthe first switching element (FET 1, 4 a) may be arranged in series withthe capacitor C₂, the second switching element being drivencomplementarily with the first switching element.

According to the present invention, the artificial line may be made in aplanar monolithic circuit technique, where the inductors and the mutualinductance are realized as coupled microstrip lines (3), and theshort-circuit which is formed in the second state of the circuitcomprises the first switching element (FET 1, 4 a) and two insulatingcrossovers (5 a, 5 b) of the microstrip lines and forms the shortestpossible transfer path between input (1) and output (2). The shortcircuit which is formed in the second state of the circuit may alsocomprise the first switching element (FET 1, 4 a), one of the coupledmicrostrip lines (3 b) and an insulating crossover (5) of a microstripline.

Furthermore, a plurality of artificial lines may be cascade-coupled witha control voltage for the entire composed artificial line being appliedto the different artificial lines in series via intermediate impedancesR, such that a respective artificial line changes its state in turn asthe control voltage increases.

According to a further advantageous embodiment, the artificial line maybe a continuously tunable artificial line by the capacitors C₁ and C₂being designed as varactors, in which a first range within which thegroup delay GD should be tunable is selected, whereupon this istransferred to a range of the cut-off frequency f₀ according to theequation $\begin{matrix}{{{{GD}(\omega)} = {\frac{2}{\omega_{C}} \cdot \frac{1 + {k\quad \Omega^{2}}}{\left( {1 - {k\quad \Omega^{2}}} \right)^{2} + \Omega^{2}}}},} & \left( {{equation}\quad 17} \right)\end{matrix}$

whereupon a cut-off frequency within this range is selected, followed bya choice of L and M at the selected frequency according to theinductance, mutual inductance and capacitance equations defined herein.Capacitances of the varactors are variable, such that the artificialline gives the delay which is intended in each moment, according toequation 17, the calculation occurring via a frequency value obtainedfrom the inductance, mutual inductance and capacitance equations definedherein. In accordance with this embodiment, the artificial line is madein a planar monolithic circuit technique, where the inductors and themutual inductance are realized as coupled microstrip lines (3), thevaractor C₁ (C_(V1)) consists of a field effect transistor (4 a) wherethe drain and source are inter-connected and the bias for tuning isapplied to its gate and the varactor C₂ (C_(V2)) consists of a fieldeffect transistor (4 b) coupled and biased in a manner corresponding tothat of the first-mentioned field effect transistor (4 a). Finally, atleast one self-switched artificial line may be cascade-coupled to thetunable artificial line.

These together with other objects and advantages which will becomesubsequently apparent reside in the details of construction andoperation as more fully hereinafter described and claimed, referencebeing had to the accompanying drawings forming a part hereof, whereinlike numerals refer to like parts throughout.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described in more detail with reference to theaccompanying drawings, in which

FIG. 1 shows a prior-art four-bit delay line with SPDT switches,

FIG. 2 is a basic sketch of an assembled artificial line according to anembodiment of the invention, which has a continuously variable delayover a large time interval,

FIG. 3a is a flow diagram of a known all-pass network,

FIG. 3b is an equivalent diagram of the all-pass network in FIG. 3a,

FIG. 4 is a diagram of ω₀GD(ω) as a function of ω/ω₀ for different Kvalues,

FIG. 5 illustrates group delay and component values as a function of thecut-off frequency,

FIG. 6 is a flow diagram of a first variant of a self-switchedartificial line according to an embodiment of the invention,

FIG. 7 is a diagram of the group delay as a function of the frequencyfor the artificial line in FIG. 6,

FIG. 8 is a flow diagram of a second variant of a self-switchedartificial line according to an embodiment of the invention,

FIG. 9 illustrates a first concrete example of a self-switchedartificial line according to an embodiment of the invention,

FIG. 10 shows a second concrete example of a self-switched artificialline according to an embodiment of the invention,

FIG. 11 shows a concrete example of a plurality of cascade-coupledartificial lines according to an embodiment of the invention,

FIG. 12 is a diagram of the group delay as a function of the appliedcontrol voltage for the cascade-coupled artificial line in FIG. 11,

FIG. 13 is a flow diagram of an embodiment of a tunable artificial lineaccording to the invention,

FIG. 14 is a diagram of the group delay as a function of the appliednegative control voltage for the artificial line in FIG. 13, and

FIG. 15 shows a concrete example of a tunable artificial line accordingto an embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Further scope of applicability of the present invention will becomeapparent from the detailed description given hereinafter. However, itshould be understood that the detailed description and specificexamples, while indicating preferred embodiments of the invention, aregiven by way of illustration only, since various changes andmodifications within the spirit and scope of the invention will becomeapparent to those skilled in the art from this detailed description.

The invention concerns basically an artificial line which in a firststate has the desired properties in respect of constant group delay in awide frequency range. The artificial line can then be accomplished as acontinuously tunable artificial line or as a self-switched artificialline.

FIG. 2 illustrates how, in one embodiment, it would be possible to builda composed artificial line which can delay signals by a total of 120 ps,the same as in the previous case of the prior-art artificial line. Hereuse is made of a tunable artificial line A as well as self-switchedartificial lines B. The continuously tunable artificial line has, independence on a control signal, a delay of up to about 20 ps. In theexample, five self-switched artificial lines are cascade-coupled to thisartificial line. The self-switched artificial line can take two distinctstates. In one state, it has a small delay, and in the other a largedelay, in the example at issue about 20 ps. The self-switched artificiallines can be controlled by a single control wire, which means aconsiderable simplification.

Below follows first a theoretical derivation of how an artificial lineof the type at issue should be designed. The self-switched artificialline follows this derivation, and the tunable artificial line takes itsstarting point in the derivation.

Both types of artificial lines are based on an all-pass network with afrequency-independent mirror impedance (constant-R all-pass network). Inthe tunable case, it is more correct to speak of essentiallyfrequency-independent mirror impedance (quasi constant-R . . . )

FIG. 3a illustrates a known all-pass network. It consists of a bridgedT-section consisting of two mutually coupled inductors of equal value L,which form the two arms, a capacitor C₂ to earth, forming the verticalarm, and a capacitor C₁ coupled over the inductors. Under specificconditions, this network becomes an all-pass network having a constantinput impedance which is independent of frequency.

To determine the scattering parameters, the T network is transformed bythe inductive coupling being drawn as a network equivalent, see FIG. 3b,where:

 L ₁ =L+M  (1)

and

L ₂ =−M  (2)

The symmetry of the circuit implies that the calculations are reduced.All scattering parameters can be derived from the reflectioncoefficients Γ_(e) and Γ₀. Γ_(e) is the result of two equal voltages ofthe same sign being applied to the two-port network. Γ₀ is the result oftwo equal voltages of opposite sign being applied to the two ports. Thescattering parameters S_(ij) for the network are obtained as follows:$\begin{matrix}{S_{11} = {S_{22} = \frac{\Gamma_{e} + \Gamma_{0}}{2}}} & (3) \\{S_{21} = {S_{12} = \frac{\Gamma_{e} + \Gamma_{0}}{2}}} & (4)\end{matrix}$

Γ_(e) and Γ₀ can be expressed in the normalized even and odd modeimpedances Z_(e) and Z₀ as $\begin{matrix}{\Gamma_{e} = \frac{1 - Z_{e}}{1 + Z_{e}}} & (5) \\{\Gamma_{0} = \frac{1 - Z_{0}}{1 + Z_{0}}} & (6)\end{matrix}$

where $\begin{matrix}{Z_{e} = {{j\quad {\omega \left( {L_{1} + {2L_{2}}} \right)}} + \frac{2}{j\quad \omega \quad C_{2}}}} & (7)\end{matrix}$

and $\begin{matrix}{Z_{0} = \frac{j\quad \omega \quad L_{1}}{1 - {2\quad \omega^{2}L_{1}C_{1}}}} & (8)\end{matrix}$

By inserting equations (5) and (6) in (3) and (4), the following isobtained: $\begin{matrix}{S_{11} = \frac{1 - {Z_{e}\quad Z_{0}}}{\left( {Z_{e} + 1} \right)\quad \left( {Z_{0} + 1} \right)}} & (9) \\{S_{21} = \frac{Z_{e} - \quad Z_{0}}{\left( {Z_{e} + 1} \right)\quad \left( {Z_{0} + 1} \right)}} & (10)\end{matrix}$

It appears from (9) that if the network has to be matched at allfrequencies, i.e. S₁₁=0 then the condition Z_(e)Z₀=1 must be fulfilledfor all frequencies. This gives after some algebra $\begin{matrix}\left\{ \quad \begin{matrix}{{L_{1} + {2L_{2}}} = {2C_{1}}} \\{{2L_{1}} = C_{2}}\end{matrix}\quad \right. & (11)\end{matrix}$

Consequently, the transmission coefficient S₂₁ becomes $\begin{matrix}{S_{21} = \frac{Z_{e} - 1}{Z_{e} + 1}} & (12)\end{matrix}$

By inserting (7) in (12), S₂₁ can be expressed as $\begin{matrix}{S_{21} = \frac{p^{2} - {ap} + b}{p^{2} + {ap} + b}} & (13)\end{matrix}$

where${p = {j\quad \omega}},{a = {{\frac{1}{L_{1} + {2L_{2}}}\quad {and}\quad b} = \frac{2}{\left( {L_{1} + {2L_{2}}} \right)\quad C_{2}}}}$

The equation (13) shows that S₂₁ has the magnitude 1 and a phaseresponse ArgS₂₁ which can be expressed as $\begin{matrix}{{ArgS}_{21} = {{- \arctan}\quad \left( \frac{\Omega}{1 - \frac{b}{a^{2}}} \right)}} & (14)\end{matrix}$

where $\Omega = \frac{\omega}{\omega_{c}}$

is the normalized angular frequency and ${\omega_{c} = \frac{b}{a}},$

where $f_{c} = \frac{\omega_{c}}{2\pi}$

is the cut-off frequency. The transfer function has a low passcharacter. The normalized circuit elements can now be expressed asfunctions of a and b. Insertion of the expressions for a and b in (12)results in $\begin{matrix}\left\{ \quad \begin{matrix}{L_{1} = \frac{a}{b}} \\{L_{2} = {\frac{1}{2}\left( {\frac{1}{a} - \frac{a}{b}} \right)}} \\{C_{1} = \frac{1}{2_{a}}} \\{C_{2} = {2\frac{a}{b}}}\end{matrix}\quad \right. & (15)\end{matrix}$

To be able to use the two-port network as a delay element, the transferphase must have a linear frequency response. In other words, the groupdelay GD(ω) must be constant with frequency. The group delay can beexpressed as follows $\begin{matrix}{{{GD}(\omega)} = {- \frac{\partial{{Arg}\left( S_{21} \right)}}{\partial\omega}}} & (16)\end{matrix}$

If (14) is inserted in (16) the following is obtained $\begin{matrix}{{{GD}(\omega)} = {\frac{2}{\omega_{c}} \cdot \frac{1 + {k\quad \Omega^{2}}}{\left( {1 - {k\quad \Omega^{2}}} \right)^{2} + \Omega^{2}}}} & (17)\end{matrix}$

where $k = {\frac{b}{a^{2}}.}$

By plotting the product ω_(c)GD(ω) as a function of Ω for different kvalues, it is easy to find the value which gives a constant group delay.This is done in FIG. 4, from which it is evident that k=0.35 is theappropriate value.

For a given transition frequency $\omega_{c} = \frac{b}{a}$

and an impedance level Z₀, one can determine explicitly the values ofthe circuit elements. They are given below as a function of the cut-offfrequency f_(c) and the characteristic impedance Z₀. $\begin{matrix}\left\{ \quad \begin{matrix}{{L\lbrack{nH}\rbrack} = {{107.4 \cdot 10^{- 3}}\frac{Z_{0}}{f_{C}\lbrack{GHz}\rbrack}}} \\{{M\lbrack{nH}\rbrack} = {{51.72 \cdot 10^{- 3}}\frac{Z_{0}}{f_{C}\lbrack{GHz}\rbrack}}} \\{{C_{1}\lbrack{pF}\rbrack} = {{27.85 \cdot 10^{- 3}}\frac{1}{Z_{0} \cdot {f_{C}\lbrack{GHz}\rbrack}}}} \\{{C_{2}\lbrack{pF}\rbrack} = {{318.3 \cdot 10^{- 3}}\frac{1}{Z_{0} \cdot {f_{C}\lbrack{GHz}\rbrack}}}}\end{matrix}\quad \right. & (18)\end{matrix}$

The values of the circuit elements, according to equation (18), and thecorresponding group delay, according to equation (17), are plotted inFIG. 5 as a function of the cut-off frequency for a device having acharacteristic impedance Z₀ amounting to 50Ω.

After this fundamental review, we pass on to study an application of afirst type of an inventive artificial line in the form of aself-switched artificial line for time delay purposes. The self-switchedartificial line can take two states. In one state, the circuit hascomponent values according to equation (18), which results in a largedelay. In the second state, the capacitor C₁ is short-circuited, whichgives a short delay.

In the known circuit according to FIG. 3a, the capacitor C₁ can beimplemented as a metal-insulator-metal (MIM) capacitor in an MMICdesign. In the self-switched artificial line, the capacitor C₁ isexchanged for a first switching element which can be described as asmall resistor in a first state (on-state) and a capacitor in a secondstate (off-state), e.g. a PIN diode, a bipolar transistor or a“switch-FET”. In the case shown in FIG. 6, the switching element is afirst field effect transistor FET 1 which is optimized to take, independence on its control voltage, two distinct states. In the one case,the transistor is biased to a conductive state, V_(G)=0. The transistorthen corresponds to a very low resistance and the circuit behaves as ashort transmission line shunted with C₂.

In the second case, the transistor is biased so as to be fully depleted,|V_(G)|>|V_(P)|, where V_(P) is the pinch-off voltage of the transistor.The transistor then corresponds to a capacitor. If the transistorparameters are selected such that the capacitance of the transistor isC₁, the circuit obtains, according to the derivation which results inequation (18), a group delay which is independent of the frequency in awide frequency range.

This results in the circuit, in dependence on the control voltage to thetransistor, taking one of two states. In the first, the group delay isvery short and in the other the delay is long, which is shown in FIG. 7.

The shunt capacitor C₂, however, is normally not small enough to give ahigh impedance to the line when the first field effect transistor FET 1is in the first state. This results in a deterioration of the scatteringproperties, especially at high frequencies. A solution to this is toconnect a second switching element, of a type similar to the first one,in series with the capacitor C₂. This second switching element is drivencomplementarily with the first, i.e. when the first is conductive, thesecond is fully depleted and vice versa. In this way, the line becomesshunted by a high impedance compared with C₂ only. FIG. 8 shows avariant of this advantageous embodiment of the invention with a secondfield effect transistor, FET 2, optimized to take, in dependence on itscontrol voltage, two distinct states, as the second switching element.

Two examples of a concrete layout for a self-switched artificial line ina planar monolithic circuit technique are shown in FIGS. 9 and 10. Inthis case, the cut-off frequency is selected to be 18 GHz and thecharacteristic impedance to be 50Ω. The desired element values are thesame in the two examples. The embodiments result in different groupdelay owing to the different geometric design of the circuits, whichwill be described below. The embodiments in the figures are drawnaccording to scale for accomplishment on a 100 μm-thick GaAs substratehaving the permitivity 12.8.

FIG. 9 shows an embodiment in which the largest possible difference ingroup delay between the two states of the circuit is desired. Thecircuit has an input 1 and an output 2. The inductances and the mutualinductance are realised as coupled microstrip lines 3. The coupledmicrostrip lines are arranged such that the short-circuited shunt formedof FET 1=4 a in the conductive state (i.e. when the circuit takes thestate with a short group delay) is the shortest possible transmissionpath between input 1 and output 2. This is achieved by using twoinsulating crossovers 5 a and 5 b. To earth extends C₂, designed as aplate capacitor 6, usually an MIM, in series with FET 2=4 b, whosesource is connected with a via hole 7 to the ground plane of thecircuit. The bias of FET 1 and FET 2 is applied to the bonding pads 8 aand 8 b, respectively, and is supplied to the gate via the respectiveresistors 9 a and 9 b which are here designed as doped channels in thesubstrate with controlled resistivity.

FIG. 10 shows an embodiment in which a smaller difference in group delaybetween the two states of the circuit is desired. The circuit has aninput 1 and an output 2. The inductances and the mutual inductance arerealised as coupled microstrip lines 3. The short-circuited shunt formedof FET 1=4 a in conductive state (i.e. when the circuit takes the statewith a short group delay) is here a comparatively longer path betweeninput 1 and output 2 by one of the coupled microstrip lines 3 b beingincluded in the shunt between the input and the output. In this caseonly one insulating crossover 5 is necessary. To earth extends C₂,designed as a plate capacitor 6, usually an MIM, in series with FET 2=4b, whose source is connected to a viahole 7 to the earth plane of thecircuit. The bias of FET 1 and FET 2 is applied to the bond plates 8 aand 8 b, respectively, and is supplied to gate via the respectiveresistors 9 a and 9 b, which are here designed as doped channels in thesubstrate with controlled resistivity.

The layout according to FIGS. 9 and 10 is cascadable, and therefore acomposed artificial line can be effected. FIG. 11 shows an example ofcascade-coupled self-switched artificial lines. By the control voltageto the respective first field effect transistor and, if necessary, therespective second field effect transistor, is applied to the differentartificial lines in series via intermediate impedances R, the respectiveartificial line changes its state in turn at an increasing controlvoltage, see FIG. 12. Thus, only one control wire is required.

Regarding a continuously tunable artificial line which can be used aloneor together with the self-switched artificial line as stated above, itcan be realised in a manner similar to that of the self-switchedartificial line. The theoretical values of the circuit elements arecalculated in a manner corresponding to the previous manner. For a givencharacteristic impedance, element values are selected by first selectinga range within which the group delay GD should be unable andtransferring, via the diagram in FIG. 5, this to a range of the cut-offfrequency f_(c). Then a cut-off frequency is selected in the middle ofthis range. L and M are selected, based on the selected cut-offfrequency, according to equation (18) and FIG. 5.

Finally the continuously tunable group delay is achieved by thecapacitors C₁ and C₂ in the two-port network according to FIG. 3a beingreplaced by varactors, see FIG. 13. The varactors are selected such thattheir capacitances C₁ and C₂ are variable and follow the curves in FIG.5 in the range for the desired variation of the group delay. Theinductances L and the mutual inductance M will not follow the relationexactly, and therefore the properties of the circuit are slightlydeteriorated. In a variation of the group delay within the range of 5-15ps, the deterioration of the input and output impedance is normallyacceptable. It is in this case more correct to speak about anessentially frequency-independent mirror impedance (quasi constant-R . .. ).

FIG. 15 illustrates an example of a layout for a tunable artificialline. The circuit has an input 1 and an output 2. The inductances andthe mutual inductance are realised as coupled microstrip lines 3. Thevoltage-controlled capacitance C_(V1) is designed as a varactorconsisting of a field effect transistor 4 a where the drain and sourceare interconnected and the bias for tuning is applied to its gate. Thevoltage-controlled capacitance C_(V2) is also designed as a varactor 4 bcomposed in the same manner as the first-mentioned varactor 4 a. Thedrain and source of this varactor 4 b are connected to the ground planeof the circuit with a via hole 7. The design uses an insulatingcrossover 5. The voltage for tuning of C_(V1) and C_(V2) is applied tothe bonding pads 8 a and 8 b respectively and is supplied to the gatevia the respective resistors 9 a and 9 b which are here designed asdoped channels in the substrate with controlled resistivity. Two MIMcapacitors 10 a and 10 b have been introduced for the varactors to bebiased.

The invention being thus described, it will be obvious that the same maybe varied in many ways. Such variations are not to be regarded as adeparture from the spirit and scope of the invention, and all suchmodifications as would be recognized by one skilled in the art areintended to be included within the scope of the following claims.

What is claimed is:
 1. An artificial line comprising a two-port networkwith an essentially frequency-independent mirror impedance, which in afirst state includes two identical inductors of magnitude L, connectedin series and having a mutual inductance M, a capacitor of magnitude C₁over the inductors and a shunt capacitor C₂ to earth, said artificialline being adapted to give a same group delay in a wide frequency rangeby element values as a function of a cut-off frequency f_(c) and acharacteristic impedance Z₀ being selected according to inductance,mutual inductance and capacitance equations$\left\{ \quad {\begin{matrix}{{L\lbrack{nH}\rbrack} = {{107.4 \cdot 10^{- 3}}\frac{Z_{0}}{f_{C}\lbrack{GHz}\rbrack}}} \\{{M\lbrack{nH}\rbrack} = {{51.72 \cdot 10^{- 3}}\frac{Z_{0}}{f_{C}\lbrack{GHz}\rbrack}}} \\{{C_{1}\left\lbrack {nF} \right\rbrack} = {{27.85 \cdot 10^{- 3}}\frac{1}{Z_{0} \cdot {f_{C}\lbrack{GHz}\rbrack}}}} \\{{C_{2}\left\lbrack {nF} \right\rbrack} = {{318.3 \cdot 10^{- 3}}\frac{1}{Z_{0} \cdot {f_{C}\lbrack{GHz}\rbrack}}}}\end{matrix}} \right.$

said artificial line being a self-switched artificial line able to takea second state with a short delay by replacing the capacitor C₁ with ashort-circuit.
 2. The artificial line as claimed in claim 1, wherein thecapacitor C₁ is a first switching element optimized to take, independence on its control voltage, two distinct states, a first statecorresponding to a capacitance of the value C₁, which gives theartificial line a long delay, and a second state corresponding to ashort-circuit with low impedance, which gives the artificial line ashort delay.
 3. The artificial line as claimed in claim 2, wherein thefirst switching element is a first field effect transistor.
 4. Theartificial line as claimed in claim 2, wherein a second switchingelement with properties corresponding to those of the first switchingelement is arranged in series with the capacitor C₂, said secondswitching element being driven complementarily with the first switchingelement.
 5. The artificial line as claimed in claim 2, wherein said lineis made in a planar monolithic circuit technique, where the inductorsand the mutual inductance are realized as coupled microstrip lines, andthe short-circuit which is formed in the second state of the circuitcomprises the first switching element and two insulating crossovers ofthe microstrip lines and forms a shortest possible transfer path betweeninput and output.
 6. The artificial line as claimed in claim 2, whereinsaid line is made in a planar monolithic circuit technique, where theinductors and the mutual inductance are realized as coupled microstriplines, and the short-circuit which is formed in the second state of thecircuit comprises the first switching element, one of the coupledmicrostrip lines and an insulating crossover of a microstrip line. 7.The artificial line as claimed in claim 1, wherein a plurality ofartificial lines are cascade-coupled and a control voltage for theentire composed artificial line is applied to the plurality ofartificial lines in series via intermediate impedances R, such that arespective artificial line changes its state in turn as the controlvoltage increases.
 8. An artificial line comprising a two-port networkwith an essentially frequency-independent mirror impedance, which in afirst state includes two identical inductors of magnitude L, connectedin series and having a mutual inductance M, a capacitor of magnitude C₁over the inductors and a shunt capacitor C₂ to earth, said artificialline being adapted to give a same group delay in a wide frequency rangeby element values as a function of a cut-off frequency f_(c) and acharacteristic impedance Z₀ being selected according to inductance,mutual inductance and capacitance equations, said artificial line beinga continuously tunable artificial line, said capacitors C₁ and C₂ beingdesigned as varactors, and a first range within which a group delay GDshould be tunable being selected, whereupon this selection istransferred to a range of cut-off frequency f₀ according to a groupdelay equation${{GD}(\omega)} = {\frac{2}{\omega_{C}} \cdot \frac{1 + {k\quad \Omega^{2}}}{\left( {1 - {k\quad \Omega^{2}}} \right)^{2} + \Omega^{2}}}$

whereupon a cut-off frequency within this range is selected, followed bya choice of L and M at the selected frequency according to saidinductance, mutual inductance and capacitance equations, capacitances ofthe varactors being variable, such that the artificial line gives thedelay which is intended in each moment, according to the group delayequation, calculation occurring via a frequency value obtained from saidinductance, mutual inductance and capacitance equations.
 9. Theartificial line as claimed in claim 8, wherein said line is made in aplanar monolithic circuit technique, where the inductors and the mutualinductance are realized as coupled microstrip lines, the varactor C₁(C_(V1)) is a first field effect transistor where drain and source areinterconnected and a bias for tuning is applied to its gate and thevaractor C₂ (C_(V2)) is a second field effect transistor coupled andbiased in a manner corresponding to that of said first field effecttransistor.
 10. The artificial line as claimed in claim 8, wherein saidartificial line is a self-switched artificial line that can take asecond state by replacing said capacitor C₁ with a short-circuit and iscascade-coupled to the tunable artificial line.